Intelligent Networked Storage Systems (A.L. N. Reddy)

This project is looking at the various architecture and performance issues in interconnecting storage devices to IP-based networks. We are investigating active storage systems, novel file system organizations that can adapt to device characteristics and application needs, flexible storage allocation and data distribution across several networked storage systems.

Protocols for extreme network environments (A.L. N. Reddy)

This project is trying to develop protocols for extreme network environments such as high-speed, high-delay networks, high-loss, low-connectivity networks. We have proposed "delayed congestion response" as a mechanism to deal with channel errors in high-loss wireless networking environments and to deal with packet reordering in wired networks. We are currently studying delay-based protocols for next generation networks.

Network Security and Service Availability (A.L. N. Reddy)

We are developing tools based on statistical techniques for analyzing network traffic in order to detect, identify and contain traffic anomalies, both at individual flow level and aggregate level. We are also studying routing techniques for improving network service availability in the presence of link and node failures during attacks.

Cross-Layer Based Rate Control for Mobile Multicast in Multimedia Wireless Networks (X. Zhang)

The goal of this project is to develop the cross-layer design based rate control schemes for mobile multicast over broadcast fading channels in multimedia wireless networks. Specifically, we aim at maximizing system throughput for mobile multicast in multimedia wireless networks while satisfying quality-of-service (QoS) requirements from different protocol layers.

Cognitive Radio MAC Protocols for Mobile Wireless Networks (X. Zhang)

The goal of this project is to design the cognitive-radio-based multi-channel medium access control (MAC) protocols for the Wireless Ad Hoc Networks. In particular, our cognitive radio MAC protocols aim at allowing the secondary users to efficiently identify and utilize the available frequency spectrum while constraining the level of interference to the primary users.

Extreme Low-power BFSK Transmitter using Subthreshold Circuits (S. Khatri)

In this project, we have fabricated a transmitter IC using sub-threshold circuits, for short range communication. We are able to achieve 25X lower power consumption compared to existing transmitters. In the future, we plan to implement a more complex IC with a on-chip receiver and microprocessor, for low power sensor node applications.

Hardware based Acceleration of Software Algorithms (S. Khatri)

In this project, we accelerate a candidate software algorithm (Boolean Satisfiability and current lookup for circuit simulation) using FPGAs and GPUs. We have shown up to 120X speedup using this idea. We have generalized this approach to accelerate any software application. The approach works efficiently and elegantly for software that performs scientific computations.

Built-In Self-Test and Self-Adaptation of Phase-Locked Loops (P. Li)

PLLs are widely used in microprocessors, SoCs and RF front-ends for on-chip clock generation and frequency synthesis. The push to deeply scaled CMOS technology has made PLLs increasingly susceptible to process variation and reliability issues. The goal of this project is to leverage the digital circuit blocks within a PLL to develop built-in self-test and self-adaptation schemes to facilitate infield test and correction of chip failures.

Adaptive design for robust and reliable VLSI circuits (J. Hu)

In this project, we will develop design and optimization techniques that make VLSI circuits capable of adjusting themselves to desired power-performance tradeoff under significant variations and aging effects.

Power-efficient non-tree clock distribution (J. Hu)

Clock distribution is an essential part of typical VLSI circuits. It consumes large amount of power and is very sensitive to variations at the same time. Non-tree based clock distribution can greatly improve robustness to variations. However, it intensifies the already large power dissipation. The focus of this project is to find new non-tree distribution approaches that can achieve variation tolerance with very limited power overhead.

Lithography-friendly VLSI circuit layout (J. Hu)

In nanometer regime, the characteristics of VLSI circuits are greatly affected by lithography process variations. These variations highly depend on circuit layout patterns, which received little attention in conventional VLSI designs. We will investigate new methods that can generate lithography-friendly layout so that lithography induced variations are largely reduced.

Large-Scale Parallel Circuit Simulation and Optimization on Multi-Core Platforms(P. Li)

Emergence of multi-core or many-core microprocessors is changing the landscape of computing. This introduces new challenges and opportunities for VLSI CAD. In this project, we develop new multi-core parallel simulation algorithms for large-scale analog/RF applications, on-chip clock and power distributions and general-purpose SPICE simulation for large custom digital ICs and memories.

Network Coding and its applications (A. Sprintson)

The goal of this project is to propose efficient algorithms for finding coding networks of minimum cost, study fundamental properties of coding networks, and study application of network coding in wireless networks.

Recovery from failures and combating malicious attacks (A. Sprintson)

The goal of this project is provide for instantaneous recovery from link failures and malicious attacks. With instantaneous recovery, the destination node is able to receive the data even if one of the links in the network fails, without any need for retransmissions or re-routing.