This presentation will describe a low power Intel(r) Architecture (IA) processor specifically designed for Ultra-Mobile PCs where average power consumed is in the order of a few hundred mW with performance similar to mainstream Ultra-Mobile PCs. The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32KB instruction and 24KB data L1 caches, independent integer and floating point execution units, x86 front end execution unit, a 512KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB). The design contains 47M transistors in a die size under 25 mm2 manufactured in a 9-metal 45nm CMOS process with optimized transistors for low leakage packaged in a Halide-Free 441 ball, 14X13 mm uFCBGA. Thermal Design Power (TDP) consumption is measured at 2W using a synthetic power-virus test at a frequency of 2GHz.

Test of phase-locked loops (PLLs) has been hampered
by the complex mixed-signal nature of the system operation.
While several built-in self-test (BIST) schemes have been
proposed to reduce the cost of PLL test, a systematic BIST
development methodology, specially targeting at the growing
parametric failures in nanometer VLSI technologies, is yet to
be developed. In this paper, we first present a detailed bottomup
parametric PLL macromodeling approach that is developed to
realistically map the device-level process variations to the variations
in system-level performances. Our parametric modeling
techniques allow us to examine the correlations between the
system performances and specific BIST measurements feasibly
through behavioral-levels simulations. By exploiting our modeling
infrastructure, an efficient methodology is then developed to
facilitate evaluation and optimization of PLL BIST schemes.
The proposed methodology is enabled by novel circuit-level
macromodeling and powerful statistical dimension reduction
techniques, the latter of which are employed to cope with the
challenges imposed by the large number of process variations that
must be considered. The application of our BIST development
methodology is demonstrated by generating optimized BIST
schemes that produce low mis-prediction levels for detection of
parametric failures of charge-pump PLLs.

In sub-100-nanometer IC technology, the process variability is a crucial issue. The process variation is due to many systematic and random factors, including design related factors such as the design pattern and the homogeneity of interconnect density, and process related factors such as manufacturing imperfections. Even though extensive efforts have been developed to reduce process variation, the percentage of variation keeps increasing as the technology nodes continuously shrink. Yield enhancement of IC circuits requires process variation to be considered, not only for post-layout simulation, but also in the very early phases of design. In a yield enhancement technology such as E-DFM, the sensitivity modeling and analysis turns out to be an efficient solution.
In this talk, the sensitivity modeling and extraction of interconnect parasitics accounting for process variation such as CMP variation and litho/etch variation is presented. The systematic (intra- and inter-die) components and the random components of the layout and process parameters after the CMP and LFD modeling are considered, respectively, during extraction and during simulation with the help of sensitivity models and netlists. The application of the parasitic sensitivity models and netlist in design optimization and in statistical simulation will also be addressed.

BIO: Dr. Zhuoxiang (Xavier) Ren works as a principal engineer at Mentor Graphics Corporation. He received his PhD in electrical engineering from